1. Field of the Invention
The invention relates generally to circuit design for serial signal clocking between circuits and more specifically relates to methods and circuit structures for source synchronous timing in exchange of signals between circuits in a system synchronous circuit platform design.
2. Discussion of Related Art
Digital electronic circuit designs have evolved over many years as complexity and density of designs both rise. Present day circuit designs permit such density that so-called “system-on-a-chip” (SOC) designs have developed in which all circuits for an entire application can be designed into a single integrated circuit package.
It is very costly to modify a large, complex, dense SOC integrated circuit design to correct errors in the logic designs. Therefore, circuit designers for such application circuits often test their logic designs long before the final SOC circuit die is designed and laid out. In testing their designs, engineers typically simulate the designs using computational simulators. Eventually, the designs are committed to some prototype circuits to test in the intended application environment. In such rapid prototyping environments, it is common to use programmable logic devices such as Field Programmable Gate Arrays (FPGAs). Since the size and complexity of an SOC may exceed the logic gate capacity of present day FPGAs it is common to use a prototyping board that is populated with multiple, interconnected FPGAs.
In implementing an SOC (or other complex circuit designs) on multiple FPGAs it is common to “partition” blocks of the application logic such that logic blocks may be distributed over various of the FPGAs. The partitioning process by the circuit designer is largely automated by computer aided engineering (CAE) tools however the designer may provide input to the CAE tools to reduce the number of signals that must be exchanged between the various FPGAs to couple the logic blocks.
A large number of signals to be exchanged between the multiple FPGAs to interconnect the logic blocks gives rise to a variety of problems. First, the number of signal pins on each interconnected FPGA used for exchange of signals may be limited based on the specifications of the selected FPGA circuits. To resolve this issue, it is known to multiplex the transfer of signals between interconnected FPGAs by serializing the multiplexed signals, transmitting the serialized data to the receiving FPGA and de-serializing the multiplexed signals at the receiving FPGA. Such serial transmission of the multiplexed signals dramatically reduces the complexity of FPGA interconnection required on the FPGAs for exchange of interconnecting signals. Many commercially available FPGA circuits include serializer/de-serializer (SERDES) circuits that may be used for this purpose. (See, e.g., Xilinx application notes “XAPP1064” and “XAPP855”).
Other problems remain even when using SERDES features of FPGAs for exchange of logic block interconnections. The serialized data transfer must be associated with some clocking mechanism. One prior technique exchanged the serial data in an “asynchronous” mode. A protocol involving handshake signals to synchronize the start of a transmission and to complete a transmission is utilized. The addition of such handshake protocols negatively impacts the maximum data rate for the exchange of the serialized signals. Slowing the data rate for the exchange of FPGA interconnect signals may impact the performance of the entire SOC circuit design prototype.
Another prior technique uses “source synchronous” clocking wherein the source of the transmitted serialized data generates a data clock and transmits its generated clock to the receiving FPGA along with the serialized data stream. The receiving FPGA may also generate a clock used within the receiving FPGA to de-serialize the received data. Generation of these clock signals within the interconnected FPGAs utilizes phase locked loop (PLL) logic within the FPGAs to generate the clock signals based on some other clock signal (e.g., a core logic clock) within the FPGA. PLL logic within the FPGAs may utilize precious resources of the FPGA logic circuits and thus consumes some of the scarce logic resources of the FPGAs. The problem of requiring a PLL in each FPGA for interconnect clocking is further exacerbated where one or more FPGAs have multiple interconnects with other FPGAs. For example, where multiple FPGAs are all interconnected with a central “control” FPGA (i.e., in a “star” topology), the central FPGA may require numerous PLL components be designed—one or more for each other FPGA with which the central FPGA is connected. Such a design requires substantial logic be dedicated within the FPGAs merely for clocking of the various interconnect signals among the FPGAs.
Thus it is an ongoing challenge to exchange signals between multiple FPGAs of an application circuit with simple structures while reducing overhead that may impact performance of the application circuit as implemented in multiple, partitioned FPGAs.